1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for forming a gate that improves the quality of the gate.
2. Description of Related Art
An embedded dynamic random access memory (DRAM) is an integrated circuit (IC) device combines a memory cell array and a logical circuit array in a single chip. The embedded DRAM, which improves the use of IC by accessing data with high speed, can be used as the logical circuit for processing data, in systems such as a graphics processor.
Conventionally, the material of the silicide layer, which is in the gate of the memory cell array, is tungsten silicide. Tungsten silicide is not suitable for the silicide layer in processes where the critical dimension is under 0.25 micron, because the resistivity of tungsten silicide is higher than titanium silicide. Processes in which the critical dimension is under 0.25 micron use titanium silicide as the material of the silicide layer formed by a self-aligned silicide (salicide) process.
FIGS. 1A-1D are cross-sectional views of a semiconductor device schematically illustrating a conventional fabrication process for forming a gate in a metal oxide semiconductor (MOS) transistor.
In FIG. 1A, isolation structures 12 are formed in a substrate 10. Then, a gate oxide layer 14 is formed on the substrate 10 by a thermal oxidation process, such as dry oxidation, wherein the substrate 10 is placed in a furnace for thermal oxidation. After the oxidation step, a polysilicon layer 16 is formed on the gate oxide layer 14 by low pressure chemical vapor deposition (LPCVD). In order to decrease the resistance of the polysilicon layer 16, boric ions are doped into the polysilicon layer 16 by an ion implantation process.
In FIG. 1B, the polysilicon layer 16 and the gate oxide layer 14 are patterned to form a gate 18. A lightly doped drain (LDD) process is performed after patterning. Then, a spacer 20 is formed on the sidewall of the gate 18, and a heavily doping step is performed to form the source and drain 22.
In FIG. 1C, a titanium metal layer 21 is formed on the gate 18 and the substrate 10 by magnetron DC sputtering deposition, wherein the thickness of the metal layer 21 is about 200 .ANG.to 1000 .ANG..
In FIG. 1D, the part of the titanium metal layer 21 that lies over the source and drain 22 and the gate 18 reacts with the silicon in the source and drain 22 and the polysilicon in the gate 18 at high temperature, to form titanium silicide. The conductive layer 24 of titanium silicide is formed on the source and drain 22 and the gate 18 by removing the other part of the titanium metal layer 21 via wet etching.
There are some problems in the MOS transistor formed by the conventional method according to the prior art. First, the resistance of the gate increases because the titanium silicide layer in the gate reacts easily with oxygen in the air at room temperature to form titanium dioxide. Second, the titanium silicide layer, formed by a self-aligned silicide process and containing an incomplete reaction product, causes instability in resistance of the titanium silicide layer. Third, the metallic impurities released from the silicide layer pollute the process equipment, wherein the metallic impurities are generated by the subsequent thermal treatment process or wet etching. Fourth, boric ions in the polysilicon layer diffuse into other devices by interconnect formed on the gate to affect the operation of these devices. Fifth, boric ions from the polysilicon layer readily penetrate into the gate oxide layer to reach the substrate, which causes the threshold voltage to decrease and the MOS transistor to operate unstably.
In light of the foregoing, there is a need to provide a method for forming a gate that improves the quality of semiconductor devices.